The present application relates generally to semiconductor device processing and equipment. More particularly, the present invention relates to a method and apparatus for monitoring the precision of wafer placement alignment when processing semiconductor devices.
Processes to define electronic devices and interconnect on and near the surface of semiconductor substrates or wafers are well known. Such processes including patterning the surface using photoresist and possibly with a hardmask material such as polysilicon or silicon dioxide, etching materials formed by photolithography using wet or reactive ion chemistry, ion implantation to define devices, chemical-mechanical polishing for planarization, and film deposition and patterning for interconnect. These processes are generally well understood and are under constant refinement to improve yield. Yield is the percentage of good semiconductor chips produced from a substrate. Good semiconductor chips are those which pass all electrical, operational and other tests and may be sold as products to customers. Yield is an important parameter of manufacturing quality. These and other processes are always being refined to allow definition of ever smaller geometries.
Two methods for achieving smaller geometries are by defining more vertically oriented devices and by improving the electrical isolation between devices. Both these methods can be employed by etching deep trenches in the surface of the semiconductor substrate. The trenches define silicon islands where devices such as transistors may be formed. In subsequent process steps, the trenches can be filled with different materials to achieve desirable effects.
For example, a trench filled with insulating material such as silicon dioxide or silicon nitride will electrically isolate adjacent silicon islands, reducing the electrical interaction of devices built therein. The deep trench can be narrower in cross section than conventional junction isolation, in which a reverse-biased diode is formed to electrically isolate adjacent areas. With the use of narrow trenches, therefore, more of the surface area of the silicon die can be used for active devices, or the total area of the die is reducing. Thus, by using the vertically-etched trench, smaller geometries are obtained.
As another example, a trench filled with a conducting layer such as polysilicon which is separated in the trench with a thin insulating dialectric can form a charge storage capacitor for a dynamic random access memory (DRAM). The plates of the capacitor are thus oriented vertically, or perpendicular to the plane of the silicon surface. This is compared to conventional metal-oxide-semiconductor capacitors formed by defining a polysilicon plate on the wafer surface and separated from the silicon substrate by a very thin layer of gate oxide. By using the vertical capacitor, smaller horizontal geometries result for the capacitor and many more capacitors, and therefore DRAM storage cells, may be built on a single semiconductor die.
Deep trenches may be formed in a silicon wafer using a deep trench silicon etch tool. One conventional method of forming deep trenches on semiconductor surfaces is by plasma etching. Plasma etching occurs in an evacuated chamber in which a wafer is placed on an electrostatic chuck (ESC) which forms the cathode of a parallel plate plasma reactor. The ESC is cooled internally by liquid cooling systems to manage the temperature of the wafer. Due to slow response time of a liquid cooling system, temperature control is frequently supplemented with a controlled cooling gas pressure on the backside of the wafer for a faster and more precise temperature control. Heat is thus carried away from the back side of the wafer through the chuck while the front side is being etched. Gases are introduced to the chamber to provide a source of ions for the etching process. Radio frequency energy is applied to drive the generation of ions and thus the formation of plasma and the etching process. A focus ring may be added to focus or concentrate the reactive ions. A computer based recipe controls the operation according to a program of instructions which reflects the required times, temperatures and other processing conditions required for etching particular films. The process may be even further automated by adding a robot which places wafers in the chamber from a previous process or storage location and removes the wafers after etching for a subsequent process step. A well designed etching process will commonly produce very high yields across the entire wafer surface.
In semiconductor processes, while reduction in yield loss is always one goal of process improvement, small levels of yield loss have been tolerated as normal. For example, yield loss is expected at the edge of the wafer, where dice are formed in the yieldable edge exclusion zone. Because of non-uniform processing conditions at the wafer edge and for other reasons, dice near the edge fail more frequently and the yield can be reduced compared to other regions of the wafer. As long as the yield loss is within acceptable tolerance, the use of the processing equipment continues. A large yield loss which is out of tolerance is not tolerated and processing equipment will be taken off line while a yield problem is isolated and corrected. In the case of intermediate yield losses, attempts at resolution are made by various unscheduled maintenance procedures. For example, in a plasma etching process, adjustments to back side cooling pressures or process gases can temporarily improve the problem.
As more aggressive process technology has extended the yieldable edge exclusion zone to less than 2 mm from wafer edge, process control on the extreme edge of the wafer has gained critical importance. For deep trench (DT) technology, control of a DT silicon etch tool is one of the most critical parameters required to achieve good edge yields. DT etch hardware limitations in particular configurations are such that the process is most aggressive on the extreme edge of the wafer. Given that DT etch has the highest aspect ratio (meaning the ratio of the depth of the trench to its cross-section width), and that both the duration and etched depth of the process are more than twice of all other DRAM etches combined, even a 1-2% difference in across wafer performance is enough to cause significant yield loss. The systematic yield loss on the edge of the wafer is further influenced by wafer placement inside the chamber when the process characteristics are such that a systematic relationship exists between process parameters such as etch rate and wafer radius.
Accordingly, there is a need for an improved method for reducing process yield loss in semiconductor processing.